PrimeTime ECO leakage recovery is available now. PrimeTime ADV provides a leap forward in designer productivity, enabling the lowest leakage power and highest frequency designs to meet today's aggressive design schedules. Increasing design functionality, timing and power closure, and rigid tapeout schedules are key challenges for signoff at new process geometries, said Jacob Avidan, vice president of engineering for static timing products at Synopsys. Complementing IC Compiler's low power and leakage optimization capabilities, PrimeTime ADV extends leakage recovery to signoff analysis, enabling lower power consumption while preserving signoff timing across multiple mode and process corner scenarios. IC Compiler uses enhanced guidance to make more informed placement and routing decisions, and to minimize the physical impact of the ECO, which results in less iterations. With knowledge of the physical environment gained in PrimeTime, improved ECO choices can be made and physical-aware ECO guidance will be provided to the place and route tool. PrimeTime ECO's scalability, with its lightweight infrastructure and its aggressive leakage recovery algorithms, tightly coupled with IC Compiler's versatility to implement the ECO guidance, is the optimal approach for advanced timing closure.īuilt on patented PrimeTime ECO technology, the new leakage and physical-aware ECO enhancements are easy to integrate into the existing flow, enabling the fastest ECO cycle in the least number of iterations. Strong ECO support with tight links between signoff timing and place and route technologies has emerged as a key requirement for our next-generation 28 nm FDSOI designs to achieve timing closure on schedule, said Indavong Vongsavady, director, Central CAD & Design Solutions at STMicroelectronics Technology R&D. These challenges stress the timing closure cycle, leading to more ECO iterations. Chips are packing more and more functionality, leading to high cell utilization complicated by stringent power and margin requirements. Nced designs using deep submicron process technology, especially those using FD-SOI and 3-D structures, are undergoing an evolution as Moore's law drives device integration, challenging performance and power scalability to keep pace.